1. Field of the Invention
The present invention relates to a memory device and an operation method thereof. More particularly, the present invention relates to a memory device for reducing an area of the memory device and enhancing an operation speed of the memory device and an operation method thereof.
2. Description of Related Art
Conventionally, the basic structure of metal oxide semiconductor (MOS) transistor has been broadly adopted in a variety of memory devices such as static random access memory (SRAM) or dynamic random access memory (DRAM) device. As the development of the semiconductor technology advances for increasing the integration of the semiconductor devices, the line width of the semiconductor device must be reduced. However, a variety of problems arise as the size of the cell of the memory device is reduced.
FIG. 1 is a schematic cross-sectional view illustrating a structure of a conventional MOS transistor. Referring to FIG. 1, the conventional MOS transistor 100 includes a substrate 102, an oxide layer 104, a gate 106, a source 108 and a drain 110. For an N-type MOS (NMOS) transistor, the substrate 102 includes a P-type substrate and the source 108 and the drain 110 are doped with N-type dopants. Alternatively, for a P-type MOS (PMOS) transistor, the substrate 102 includes a N-type substrate and the source 108 and the drain 110 are doped with P-type dopants. In general, the source 108 and the drain 110 are doped by thermal diffusion method or ion implantation method. The oxide layer 104 includes such as silicon oxide SiO2, and the gate 106 includes metal. As shown in FIG. 1, the voltages applied to the substrate 102, the gate 106, the source 108 and the drain 110 are represented as Vsub, Vg, Vs and Vd respectively.
Hereinafter, the operation of the MOS transistor illustrated in FIG. 1 will be described. Referring to FIG. 1, it is assumed that the MOS transistor 100 is an NMOS transistor. When the gate voltage Vg≦0, even though the source voltage Vs or the drain Voltage Vd is not zero, the current between the source 108 and the drain 110 is extremely small and can be ignored. Therefore, the source 108 and the drain 110 is regarded as being isolated, and thus the NMOS transistor is turned off. When the gate voltage Vg>0 and larger than the threshold voltage Vt, the junction between the oxide layer 104 and the substrate 102 is strongly inverted to be an N-type channel. Therefore, the source 108 and the drain 110 are conducted, and thus the current between the source 108 and the drain 110 is not equal to zero, therefore the NMOS transistor is turned on.
FIG. 2 is a block diagram illustrating a memory cell of a conventional DRAM device. Referring to FIG. 2, a memory cell 200 includes an NMOS transistor 202, a capacitor 204, a bit line B and a word line W. The gate of the NMOS transistor 202 is connected to the word line W, the source of the NMOS transistor 202 is connected to the bit line B, and the drain of the NMOS transistor 202 is connected to the capacitor 204.
FIG. 3 is a schematic cross-sectional view illustrating a structure of the memory cell of the DRAM device shown in FIG. 2. Referring to FIG. 3, the gate 306 of the NMOS transistor 202 is connected to the word line W, the source 308 of the NMOS transistor 202 is connected to the bit line B, and the drain 310 of the NMOS transistor 202 is connected to the capacitor 204. In addition, the substrate 302 is a P-type substrate, and the source 308 and the drain 310 are dopes with N-type dopants.
As the line width of the memory device is reduced, the channel length between the source and the drain (e.g., the distance L1 shown in FIG. 1 or the distance L2 shown in FIG. 3) is also correspondingly reduced leading to a short channel effect due to reduction in the threshold voltage Vt and increase in the sub-threshold current. In addition, the shorting of channel length also leads to generation of hot electron effect due to increase in the electric field between the source and the drain. Therefore, the amount of the carriers in the channel near the drain is increased, and thus an electrical breakdown effect may be generated in the MOS transistor. Thus, generally the channel length has to be long enough to prevent a punch through effect. Accordingly, as the size of the MOS transistor or the memory device is minimized, the conventional design thereof is not applicable.